1. Field of the Invention
The present invention relates to a method and structure for improving the efficiency and linearity of a power amplifier (PA). More specifically, the present invention relates to a method and structure for turning off a subset of the transistors in a power amplifier during low power operation.
2. Related Art
Linear power amplifiers are often operated in class AB mode. Operation in class AB mode provides for reduced power supply current to the power amplifier as the power of the input signal is reduced. The power supply current can be reduced until a minimum quiescent current is reached. The direct current (DC) power to radio frequency (RF) power efficiency degrades as the power of the input signal is reduced. Prior art linear power amplifiers provide some improvement in low power efficiency by stepping the quiescent current to a lower level for low power operation. However, the linearity of the power amplifier is degraded at very low quiescent current levels.
FIG. 1 is a circuit diagram illustrating a conventional power amplifier 100, which includes amplifier stages 101–102 and associated bias circuits 111–112. Each of amplifier stages 101–102 includes a parallel-connected set of NPN bipolar transistors 103–104, respectively. Ballast resistors 105–106 are connected to the bases of transistor sets 103–104. In general, the bases of transistor sets 103–104 are configured to receive a radio frequency input signal (e.g., RFIN). The emitters of transistor sets 103–104 are coupled to ground, and the collectors of transistors sets 103–104 are configured to provide an RF output signal (e.g., RFOUT) to an output terminal of the associated amplifier stage.
When the input signal RFIN is controlled to be a high power signal (i.e., during high-power operation), a HI/LO control signal is activated to a first logic state. In response, bias voltage control circuits 111–112 provide relatively high bias voltages VBIAS1–VBIAS2. As a result, amplifier stages 101–102 operate in a linear manner in response to the RFIN signal. Conversely, when the input signal RFIN is controlled to be a low power signal (i.e., during low-power operation), the HI/LO control signal is deactivated to a second logic state. In response, bias control circuits 111–112 provide relatively low bias voltages VBIAS1–VBIAS2. Under these conditions, amplifier stages 101–102 consume less power, but the linearity of power amplifier 100 is degraded under these conditions.
It would therefore be desirable to have an alternative to the extremely low quiescent current operation (i.e., “current starved” operation) that results when the power supply current to the power amplifier is reduced as the power of the input signal is reduced.